1. Field of the Invention
This invention relates to an improved integrated circuit structure. More particularly, this invention relates to an improved integrated circuit structure having compensating means for self-inductance effects and a method of forming the compensating means.
2. Description of the Related Art
With advancement in process technologies, very large scale integrated circuit (VLSI) structures are becoming increasingly denser, larger, and faster. Such structures require many output pins to switch simultaneously. Also, with increasing clock speeds, the pins need to switch very quickly, i.e., within 20-30 nanoseconds or even faster. Due to system and testing requirements, the capacitive loading on these pins is 100 to 150 pf. All of these factors combine to make very high peak current requirements on the Vcc and Vss busses. These peak currents can make voltage spikes on the Vcc and Vss busses large enough to cause malfunctions in the chip logic. Also the voltage levels of non-switching outputs can be degraded while a large number of other outputs are switching.
With faster switching times, longer power and ground paths due to larger die size, and larger packages to house larger devices, inductive voltages encountered during switching, due to the self-inductance of power busses, bond wires and package leads, becomes important. Such induced voltages can adversely effect switching speeds and can result in noise spikes on the Vcc and Vss busses which can, in turn, cause soft errors.
It has been proposed to solve or alleviate the problems caused by voltage spikes induced by the inductance in the busses and leads by slowing down the outputs, increasing the widths of the Vcc and Vss busses, increasing the number of power pads, providing separate power pads for input and output, changing the pin-out configuration, or changing the package type.
Unfortunately, each of these solutions involves other problems. Slowing down the outputs can affect the AC timing while increasing the widths of the busses will have a limited positive effect on the self-inductance effect. More power pads and/or separate power pads for input and output will result in a higher pin count which can raise the package cost. Existing pin-out definition may also limit the addition of more power pads or the changing of pin-out configuration. Changing of the package type may be limited by the package type used in an existing product.
It would, therefore, be desirable to provide an improved integrated circuit structure wherein the problems of induced voltages and high current needs would be alleviated or compensated for.